1. Field of the Invention
This invention relates to a semiconductor memory device such as a mask ROM (Read Only Memory), an EPROM (Erasable Programmable ROM) or an SRAM (Static Random Access Memory), and more particularly relates to a semiconductor memory device having an improved data read circuit.
2. Description of the Prior Art
In a semiconductor memory device, since data read out from a memory cell is a weak signal, the signal is amplified on an output signal line by a sense amplifier and then output. If the sense amplifier is always in an active state, the power consumption of the semiconductor memory device becomes too large. Therefore, in a conventional mask ROM or the like, after data read out from a memory cell is amplified by a sense amplifier and the read-out data becomes valid internally, the valid data is latched in a latch circuit. Thereafter, the sense amplifier is in an inactive state until the next read, whereby the power consumption is reduced.
A data read circuit in a mask ROM of the above-mentioned configuration is shown in FIG. 7. A memory cell 1 is arranged at each crossing of a number of word lines 2 and bit lines 3. Data stored in the memory cell 1 is input into a sense amplifier 6 through a bit line 3 via an FET 5 which is controlled by a column selection line 4. The data S.sub.OUT amplified by the sense amplifier 6 is latched in a latch circuit 7 and output via an output circuit 8 as output data D.sub.OUT of the ROM.
In this case, the sense amplifier 6 and the latch circuit 7 receive a sense signal .PHI..sub.SA and a latch signal .PHI..sub.LT from a timing generator (TG) circuit 9, respectively. As shown in FIG. 8, when the TG circuit 9 detects the change of an address signal A, the sense signal .PHI..sub.SA becomes High to activate the sense amplifier 6. The latch signal .PHI..sub.LT is at a High level during a short time period after the read-out data becomes valid internally, so as to allow the latch circuit 7 to latch the data S.sub.OUT output from the sense amplifier 6. When the data S.sub.OUT is latched at the rise of the latch signal .PHI..sub.LT, the sense signal .PHI..sub.SA returns to Low so that the sense amplifier 6 is inactivated, whereby the power consumption of the sense amplifier 6 is suppressed until the next read. The read-out data latched in the latch circuit 7 can be output from the output circuit 8 as the output data D.sub.OUT for a predetermined period.
However, in the above configuration, in the case where the address signal A does not change at the first access after the power source V.sub.cc is turned on as shown in FIG. 9, the TG circuit 9 can not output the sense signal .PHI..sub.SA and the successive latch signal .PHI..sub.LT, so that the output data D.sub.OUT continues invalid. In this case, the operation must be performed in such a complicated manner that a dummy cycle is carried out in order to change the address signal A after power is turned on, and then the regular address signal is output as shown in FIG. 10.
In the above-mentioned configuration in which the data read from the memory cell 1 is latched in the latch circuit 7 once and then output, when erroneous data is latched by a noise on a power supply line etc., the erroneous data is output as the output data D.sub.OUT, without conversion.
As described above, a conventional semiconductor memory device has problems in that it requires a dummy cycle when the system is powered on, in order to suppress the power consumption of the sense amplifier 6, and that the probability of a data read error is prone to increase.